The present invention relates to digital logic circuits in the form of structured logic arrays, and more particularly, to structured logic arrays which can be implemented using MOS integrated circuit technology to dynamically execute the steps of a Boolean function.
The general design and operating principles of a structured logic array, also sometimes referred to as a storage or stored logic array, are disclosed in U.S. Pat. No. 4,068,214, issued to Suhas S. Patil, the disclosure of which is hereby incorporated by reference. The array basically comprises a plurality of orthogonally disposed column and row conductors. Each group of conductors comprising a column is associated with a Boolean variable, and the electrical potentials of the conductors represent the logical state of the variable. Each row in the array performs the function of a Boolean implicant, or a conjunction term. The rows and columns of the array are interconnected in accordance with one or more Boolean functions by means of cell networks. The cell networks connect column output conductors to a row by means of logical conjunctive (AND or NAND) connections, and connect the column input conductors to a row by means of logical disjunctive (OR or NOR) connections. By arranging the cell networks to interconnect the columns and rows in accordance with one or more predetermined Boolean functions, the structured logic array can produce predetermined output signals in response to a predetermined input signal or set of signals.
Such a structured logic array can be constructed in a programmable format. The cell networks can be connected to the conductors of the columns and rows by means of discretionary contacts which enable the cells to be selectively interconnected between the rows and columns of the array in accordance with one or more predetermined Boolean functions. In addition, the row and column conductors can have discretionary contacts periodically disposed along their lengths to enable the rows and columns to be segmented, to thereby enable a plurality of independent functions to be executed.
The previously cited patent application further discloses that each cell network can comprise a logic network, and at least some of the cells can also include a storage network. The columns connected to the cells having storage elements are thereby equipped with memory capabilities.
Structured logic arrays such as those disclosed in the previously mentioned patent and patent application have a number of advantages over prior art programmed logic arrays and other forms of digital memory circuits, such as ROM's, for example. The structured logic array can be segmented to perform a number of independent tasks, thereby providing an increased degree of versatility in program execution, and hence increased applicability over prior art circuits. The structured logic array does not require extra program steps to extract and combine non-uniform sized data fields, a drawback inherent to the prior art systems. In addition, the structured logic array is capable of executing a number of actions simultaneously, rather than sequentially.
A further advantage of the structured logic array lies in the increased perception it affords the initial circuit designer into the considerations involved in the physical layout of the circuit. In the design and construction of many logic circuits, the initial designer formulates a circuit, using logic elements, to perform a desired function. An engineer familiar with the mechanics of constructing circuits then prepares the physical layout for the designed circuit, utilizing actual electronic components which make up the logic elements. The initial designer is concerned with the functional aspects of the circuit while the layout engineer is interested in placing all of the necessary electronic components within a predetermined amount of space in an operative arrangement, and quite often each person is not aware of the other's concerns in the design of the circuit, which can result in less than optimum efficiency in circuit design. However, the structured logic array provides the initial designer with a perception of the circuit layout, thus affording a more efficient concept for circuit design.
In the past, logic arrays, including structured logic arrays, have been designed as static circuits which require a source of a continuous DC voltage signal for constantly supplying power to all of the components in the circuit. For example, the previously cited patent application discloses a specific circuit implementation of a structured logic array using I.sup.2 L circuit technology. It will be readily appreciated that the need to continuously supply DC power to all of the components of the array is undesirable from an economic standpoint, particularly for large array circuits. In addition, the speed with which logic functions can be carried out in a static circuit is limited due to the presence of load devices which are inherent to static circuits and which limit the current available to perform switching operations. If the load devices in the circuit are made larger to reduce their resistance and thereby increase the current available to charge circuit capacitance, then the size of the switching transistors in the array for discharging, or pulling the capacitance to ground, must also be increased to enable them to carry the larger current. Larger transistors increase the capacitance in the circuit, and therefore the switching speed of the circuit remains limited due to the additional time necessary to charge and discharge the larger capacitance.
Furthermore, the speed with which logic functions can be performed in a static array is inversely proportional to the size of the array. As the number of columns and rows in the array are increased, the switching speed of the array as a whole decreases. Thus, for a logic array of any practical size, the available switching speed is limited to a degree which renders use of the array infeasible except in limited applications where slow switching speeds can be tolerated.
It is therefore a general object of the present invention to provide a novel structured logic array which overcomes the need to provide a continuous DC power signal throughout the rows and columns of the array.
It is another object of the present invention to provide a novel structured logic array which operates at least partially in a dynamic mode to thereby decrease power requirements.
It is a further object of the present invention to provide a novel method for dynamically executing a Boolean function.
It is yet another object of the present invention to provide a novel structure which enables the size of a logic array to be increased over static circuits without significantly affecting the speed with which operations can be carried out in the array.
It is yet a further object of the present invention to provide a novel structured logic array which achieves the foregoing objects through the use of integrated circuit technologies, and in its preferred embodiment MOS technology, to thereby utilize, in an advantageous manner, the high input impedance and stray capacitance inherent to such circuits.